Vladimir V. Belyaev
Principal Back-End ASIC Designer &
Layout Artistdownload as PDF

15 years of expertise in Physical Back-End IC development:
Analog IC Layout, RTL-2-GDS; Flows and Methodology;
CAD-support: PDK development (P-cells, Tech-LEF, OA techDB).

IVA TECHNOLOGIES

Principal Back-End Engineer / Physical Design Engineer

Dec 2018 - present

🇷🇺 Moscow, Russian Federation

Collateral download, installation, organisation and maintenance.
Installation and setup of CAD tools.
RTL-to-GDS implementation:
Logic Synthesis, Memory Compilers (Dolphin, TSMC, Synopsys), Formal Verification, SDC, floorplanning, power-planning, CTS, P&R, STA.
Sign-off: DRC, LVS.
successful tape-out of TPU (Tensor Processing Unit) chip for neural networks acceleration on tsmc28hpc+.
Logic synthesis of “Tiny TPU” and “TPU v3” on tsmc16ffc, gf22fdx.
Benchmarking of different technologies and library sets.
CAD scripting:
TCL:
‣ calculate maximum cell frequency out of the Liberty file;
‣ generation of mmmc.tcl for with all available corners (Cadence Genus flow);
‣ generation of Timing and Power reports for the given list of analysis views in CSV and HTML formats;
Python:
‣ GDSII date accessed and date modified changer;

MOSCOW STATE UNIVERSITY / MALT SYSTEM

Back-End Engineer / Physical Design Engineer / Analog Layout Designer

Aug 2016 – Dec 2018

🇷🇺 Moscow, Russian Federation

RTL-to-GDS implementation:
Logic Synthesis, Formal Verification, SDC, floorplanning, power-planning, CTS, P&R, STA.
Sign-off: DRC, LVS.
Tools: Cadence Genus Physical with Stylus Common UI, Cadence Innovus with Common UI, Cadence Conformal Mentor Graphics Calibre LVS, DRC, xACT, PEX, DRV.
participated in tape-out of “MALT-Cv1” processor for blockchain applications on TSMC28HPC+;
successful tape-out of “Correlator” ASIC on Silterra C18G technology.;
Post-layout Spice Simulation, Monte-Carlo Simulation, Mixed-signal Simulation.
R’n’D activity on back-end optimization for ultra-low power cryptographic and blockchain application:
Layout Development of custom standard cells and digital logic blocks:
‣ CPL logic gates;
‣ full-adder;
‣ half-adder;
‣ 32-bit custom CPL adder;
Layout Development of custom Analog IP blocks: Digitally-controlled ring oscillator at 500MHz, Power-on-reset.
(Layout were developed for LN10LPP, GF22FDX, TSMC16FFC)
Analog Layout Developed:
‣ Developed 8-bit SAR ADC layout on TSMC28HPC+ technology.
‣ Successful tape-out of 8-bit SAR ADC test chip.
CAD support for IC technology developed in Soviet Union, technology node 1u:
set of Cadence skill p-cells was developed ( including regular and ring-type gate MOS transistors, resistors with number in series, number in parallel functionality); Cadence OA technology file was improved to support Virtuoso Space-based Router. It dramatically reduced the layout development cycle.
CAD scripting:
Python:
‣ gds2svg converter;
‣ gds2msk & msk2gds convertor Microwind ⇔ GDSII.

NXP SEMICONDUCTORS

PDK Engineer

Sep 2015 – Feb 2016 • 6 mos

🇳🇱 Nijmegen, Netherlands

TechFile, TechLEF development;
front-end development of new device class – stacked ESD MOSes within 40nm PDK.

FREESCALE SEMICONDUCTORS

Oct 2007 – Aug 2015 • 7 yrs 11 mos

🇷🇺 Moscow, Russian Federation

Senior Layout Designer

Jan 2015 – Aug 2015 • 8 mos
Analog layout development on 180nm high voltage technology with Virtuoso XL, Calibre LVS, DRC, MRC, Tiling.
Achievements: Two successful tapeouts.

Senior PDK Engineer

Aug 2013 – Feb 2014 • 7 mos
Technology Database development and support for Freescale and 3rd-party PDK;
technology LEF development.
Maintain consistency between TechLEF and TechDB.
RTL to GDS Flow development, support and testing.
Achievements:
‣ Deployed Dynamic Abstract capability for Freescale PDKs;
‣ Leaded Encounter Tiling development;
‣ Integrated cadence PVS with the tiling deck from TSMC into Encounter for 28nm and 16nm processes to allow signoff-quality tiling within Encounter and proper timing assessment;
‣ 4 bug CCR for Cadence Encounter and 2 enhancement request CCR for PVS;
‣ Enabled Voltage aware P&R in Cadence Virtuoso and VSR by Voltage-dependent spacing constraints;

Senior PDK Engineer

Feb 2014 – Jan 2015 • 1 yr
Pcell development within PDK team.
Pcell development and testing using Skill language.

PDK Validation Engineer

Oct 2007 – Aug 2013 • 5 yrs 11 mos
PDK Validation (Cadence IC package both cdba & OA, Soc Encounter, QRC, Voltage Storm, Abstract generator, DRD. Mentor Graphics tools (Calibre DRC, LVS, DRV, PEX). Freescale tools)
Communication with colleagues across the globe: PDK Flow Validation team India, customers and developers in US, Israel. Development of new testing tasks, testing flows and methodologies.
Driving automation: enhancement requests for the automation team, self-made scripts.
Ownership of cmos45soi (45nm), cmos32soi (32nm), TSMC's cln40lp (40nm), cln28hp (28nm).
Leadership over intern colleague: help in team integration, lot of training with CAD tools, design flows, methodologies etc.
Leadership over the PDK Validation team during owned PDK's testing: (Creation of Validation Plan, downloading and installing PDK, setting up the environment, tool versions, distribution of the testing tasks across the team, driving meeting the deadline in tight schedule, communication with developers, creating postmortem reports, presentations).
Lead Continuous Validation Improvement program (Analyzing incoming Bug tickets and closure of Validation gaps).
Worked with Physical Verification Team to create DRC and MRC QA cells.
Achievements:
‣ Input quality control done for cmos32soi, cln28hp and cln40lp 3rd party PDKs allowed proper resource assessment and enabled development activities for Freescale internal PDK solutions;
‣ Develop express testing methodology for foundry PDKs;
‣ Technology LEF verification on design IP newsletter creation to present PDK Validation team innovations for the entire company ‣ Expertise in parasitic extraction flow;
‣ Developed LVS-LPE flow for cln40lp technology;
‣ Developed Tiling script for SOC Encounter supplied with Cmos45soi PDK;
‣ Developed SOC Encounter automated flow for PDK testing using shell and TCL scripting allowed to reduce testing time;
‣ 🇷🇺 Moscow machines benchmarking methodology was developed and performed;
‣ Collaboration with design team - performed preliminary DRC assessment of developing IP on cln40lp technology;
‣ Personal “Winning Starts Here” award, Team award for Contribution in the Quality.;

CADENCE DESIGN SYSTEMS

Back-End CAD Validation Engineer

May 2007 – Aug 2007 • 4 mos

🇷🇺 Moscow, Russia

Test flows processing (SOC Encounter, Virtuoso, Assura, PVS, CCO. A variety of tools for IC design automation)
csh and encounter text command scripting (TCL)
Preparation of testcases, writing PCR’s
Achievements:
‣ got familiarity with encounter TCL scripting;
‣ got familiarity with CVS Versioning system;
‣ got ownership over largest test flow in the team;

UNIQUE ICS

Layout Engineer

Jun 2005 – May 2007 • 2 yrs

🇷🇺 Moscow, Russia

Digital and analog layout development (Virtuoso layout editor, SOC Encounter);
Chip-level SOC design, IO cells layout design, digital cells layout design;
Layout verification (Cadence, Mentor Graphics tools DRC, LVS, LPE).

INTEL

Promoter

2001 – 2002 • 2 yrs

🇷🇺 Moscow, Russia

Intel representative in Intel Demo Days activity.
(Common Intel and Microsoft program. Advertisement of released Pentium 4 CPU's together with Microsoft Windows XP OS, leading of demo-stand in large trading centers of 🇷🇺 Moscow).
Responsibilities: provide potential customers with information about Intel innovative CPU's, presentations and technical demonstrations using various software packages. Provide information about features of released OS, propagate information about advantages of the genuine software.
Skills:
‣ Deep knowledge of IBM PC architecture and hardware;
‣ CPU architecture fundamentals;
‣ Practical experience with a number of software applications;
‣ Excellent communication.

MIET - NATIONAL RESEARCH UNIVERSITY OF ELECTRONIC TECHNOLOGY

M.Sc. in Technics and Technology of Electronics and Microelectronics.

1999 - 2005

🇷🇺 Moscow, Russian Federation